Welcome! I’m an MIT sophomore studying Electrical Engineering & Computer Science (6-5) and Mathematics (18), minoring in Linguistics (24). I focus on programming languages and computer architecture, with interests in performance engineering, compilers, ML, and numerical methods. I especially like making Python eDSLs, and I’ve recently gotten slightly obsessed with Asahi Linux, Nix, and Apple silicon.
Outside of school I enjoy language learning, amateur radio, music, nature, and reading.
Projects
Hardware / Compilers / Systems
- ParaDPLL - FPGA SAT Solver written in SystemVerilog for 6.205 final project, somewhat optimized.
- Finesse - Python FSM eDSL and toolkit including visualzation, optimization, and SystemVerilog codegen (used to make ParaDPLL visualizations).
- TinyIR - Functional Python GPU IR, with JAX, Numpy, Torch.func, and other backends.
- Split Stenography Keyboard - Custom low profile split keyboard for stenography and standard QWERTY layout.
- M1 Secret Extensions (Coming Soon) - Enable and reverse engineer undocumented ISA extensions for Apple silicon, used for implementing Rosetta 2 fast user space x86 emulation.
- Apple optimized FEX-Emu (Coming Soon) - Implementing some Rosetta 2 optimizations into FEX-Emu, using reverse engineered Apple silicon x86 emulation hardware support.
ML / Game AI / NLP
Math
Random