Welcome! I’m an MIT sophomore studying Electrical Engineering & Computer Science (6-5) and Mathematics (18), minoring in Linguistics (24). I focus on programming languages and computer architecture, with interests in performance engineering, compilers, ML, and numerical methods. I like making Python eDSLs, and I’ve recently gotten slightly obsessed with Asahi Linux, microarchitecture reverse engineering, and Apple silicon.
Outside of school I enjoy language learning, amateur radio, music, nature, and reading.
Projects
Hardware / Systems
- ParaDPLL - FPGA SAT Solver written in SystemVerilog for 6.205 final project.
- M1 Undocumented Extension Enabler - Kernel module enabling undocumented Apple ARM64 ISA extensions on Linux, used to implementing Rosetta 2 fast userspace x86 emulation.
- Memory Ordering Instructions - A writeup on explicit memory ordering instructions on Intel x86 64 and ARMv8-A+.
- Finesse - Python FSM eDSL and toolkit including visualzation, optimization, and SystemVerilog codegen (used to make ParaDPLL visualizations).
- TinyIR - Functional Python GPU IR, with JAX, Numpy, Torch.func, and other backends.
- Apple optimized FEX-Emu (Coming Soon) - Implementing some Rosetta 2 optimizations into FEX-Emu, using reverse engineered Apple silicon x86 emulation hardware support.
- Prefetch Research (Coming Soon) - Researching builtin prefetch behavior and fine-grained cache line control on various microarchitectures.
ML
Math
Random